The present invention relates to an encoder and a driving device incorporating the same.
Japanese Patent Publication No. 63-69323A discloses an encoder circuit which comprises 2n detectors for detecting a mark provided on a moving plate for moving relatively and outputting signals having 2n phases shifted from each other by 90/2n degrees (n is an integer of 2 or more). The encoder circuit further comprises a resolution subdividing circuit to which the signals having the 2n phases are inputted and a stage, in which the signals are output to a latter step from separate exclusive-OR circuits to which respective sets of outputs of a former step having phases shifted from each other by 90 degrees is inputted, is repeated by n-times.
In the case where the signals having the 2n phases shifted from each other by 90/2n degrees (n is an integer of 2 or more) which are output from the 2n detectors are integrated by the exclusive-OR circuits in the n-stages as described the above, however, the signal output from a final stage of the exclusive-OR circuits has a frequency which is 2n-times as high as the signal output from the detector. As a result, the encoder circuit itself and a circuit such as a control board for receiving a signal output from the encoder circuit must be adapted to process such a high frequency signal,
In addition, in the above encoder circuit, the signals having the 2n-phases shifted from each other by 90/2n degrees (n is an integer of 2 or more) are generated one by one through 2n separate detectors. For this reason, there is a possibility that the chronological order of the level change points of the output signals of the 2n detectors might not be obtained in an assumed order because of relative precision in positions in which the detectors are to be provided. As a result, there is also a possibility that the chronological order of the level change points in the signals output through the n-stages of exclusive-OR circuits might not be obtained as assumed.
If the relationship between the positions in which two detectors having output signals synthesized through the exclusive-OR circuit are disposed is not relatively proper, for example, a difference in the phase between the output signals is deviated from 180 degrees so that a duty of the output signal is greatly deviated from 50%.
In the case where an encoder circuit is used for detecting the feeding amount of a medium in a printer, particularly, the medium feeding is PID (Proportional, Integral and Differential) controlled corresponding to a moving distance and a speed. Consequently, a frequency of a signal output from each of the detectors is greatly changed within a range from a low frequency at a low feeding speed to a high frequency at a high feeding speed. In order to shorten a time required for feeding the medium, moreover, it is required that a maximum feeding speed is to be increased as greatly as possible.
In the case where the detectors are provided separately as described in the above publication, there is also a possibility that the chronological order of the level change points of their output signals might be different from that obtained at a low frequency when the frequencies of the output signals are changed from “low” to “high” with an increase in the medium feeding speed. In other words, the chronological order of the level change points cannot be guaranteed between the output signals.
These problems become remarkable when a level change point for one output signal is increased to enhance a detecting resolution of a position or a speed so that the output signal has a frequency increased.